Power semiconductor products are often fabricated using N or P channel drain-extended metal-oxide-semiconductor (DEMOS) transistor devices, such as lateral diffused MOS (LDMOS) devices, for high power switching applications. DEMOS devices advantageously combine short-channel operation with high current handling capabilities, relatively low drain-source on-state resistance (Rdson), and the ability to withstand high blocking voltages without suffering voltage breakdown failure. Breakdown voltage is typically measured as drain-to-source breakdown voltage with the gate and source shorted together (BVdss), where DEMOS device designs often involve a tradeoff between breakdown voltage BVdss and Rdson. In addition to performance advantages, DEMOS device fabrication is relatively easy to integrate into CMOS process flows, facilitating use in devices where logic, low power analog, or other circuitry is also to be fabricated in a single integrated circuit (IC).
N-channel DEMOS transistors are asymmetrical devices in which a p-type channel region is typically formed in a p-well between an n-type source and an extended n-type drain. Low n-type doping on the drain side provides a large depletion layer with high blocking voltage capability, wherein the p-well is typically shorted to the source by a back-gate connection to prevent the p-well from floating, thereby stabilizing the device threshold voltage (Vt). To address high breakdown voltage requirements, the device drain region is spaced from the gate to provide a drift region or drain extension in the semiconductor material therebetween. The drain extension or drift region between the channel and the drain is typically made (implanted or diffused) to a relatively shallow depth with only moderate or light doping, and is sometimes referred to as a reduced surface field (RESURF) implant region. The spacing of the drain and the gate spreads out the electric fields in operation, thereby increasing the breakdown voltage rating of the device (higher BVdss). However, the drain extension increases the resistance of the drain-to-source current path (Rdson), whereby DEMOS device designs often involve a tradeoff between breakdown voltage BVdss and Rdson.
DEMOS devices have been widely used for power switching applications requiring blocking voltages in the range of 20-60 volts, and current carrying capability in the range of about 1-3 amps or higher, particularly where a solenoid or other inductive load is to be driven. In one common configuration, two or four n-channel DEMOS (DENMOS) devices are arranged as a half or full “H-bridge” circuit to drive an inductive load. In a half H-bridge arrangement, two DENMOS transistors are coupled in series between a supply voltage VCC and ground with a load coupled from an intermediate node between the two transistors to ground. In this configuration, the transistor between the intermediate node and ground is referred to as the ““low-side” transistor and the other transistor is a “high-side” transistor.
FIGS. 1A and 1B illustrate a portion of a conventional driver IC that includes drain-extended MOS devices to drive an external inductive load. FIG. 1A illustrates a full H-bridge device 2 powered by a DC supply voltage VCC. The device 2 includes four DENMOS devices T1-T4 having corresponding sources S1-S4, drains D1-D4, and gates G1-G4, respectively. The transistors are arranged as two pairs of high and low-side drivers with the load coupled between the intermediate nodes of the two pairs, thereby forming an “H-shaped” circuit. On the left side of the H-bridge, a low-side driver T1 and a high-side driver T2 are coupled in series between the supply voltage VCC and ground, and the other pair T3 and T4 are similarly connected (high and low). The transistor T2 has a drain D2 coupled to VCC and a source S2 coupled with an intermediate node N1 at the load. The low-side transistor T1 has a drain D1 coupled to the node N1 and a source S1 coupled to ground. The node N1 between the transistors T1 and T2 is coupled to a first terminal of an inductive load and the other load terminal is coupled to the other transistor pair T3 and T4, wherein the load is typically not a part of the device 2. The high and low side transistor gates are controlled so as to drive the load in alternating fashion. When the transistors T2 and T4 are on, current flows through the high-side transistor T2 and the load in a first direction (to the right in FIG. 1A), and when the transistors T3 and T1 are both on, current flows through the load and the low-side transistor T1 in a second opposite direction.
As shown in FIG. 1B, the transistors T1 and T2 are fabricated as DENMOS devices, wherein parasitic diodes and NPN transistors are incidentally formed therein (illustrated in dashed lines for the low-side device T1). The low-side driver T1 includes a parasitic back-gate diode D1 and a parasitic NPN transistor 44. The diode D1 has an anode connected to the source S1 and a cathode connected to the drain D1. The parasitic NPN transistor 44 has an emitter coupled to the node N1 between the low and high-side transistors T1 and T2, as well as a base and collector coupled to ground. The device 2 is formed in a P-epi silicon substrate 4 with a p+ doped contact region 52 disposed at an upper surface of the substrate 4. Two n+ buried layers (NBL) 8a and 8b in the substrate 4 provide isolation for the low and high-side devices T1 and T2, respectively, where the buried layer 8b for the high side device T2 is coupled to VCC and layer 8a of the low-side device T1 is grounded.
Upper epitaxial portions of the substrate 4 are p-doped to form P-BASE regions 6a and 6b within the isolation layers 8a and 8b, respectively. A p-well 18a is formed within the P-BASE 6a, and a source S1 is formed in the well 18a, including n+ portions 64a and a p+ back gate 65a. An n+ drain 56a (D1) is formed in the P-BASE 6a, which is spaced from the p-well 18a, and an n-RESURF region (e.g., drain extension or drift region) 22a extends from a channel portion of the P-BASE 6a under a gate 42a (G1) to the drain 56a. An oxide layer 71 is provided on the drift region 22a, and the gate 42a operates to provide a field in the underlying p-doped channel. The high-side driver T2 includes similar structures including a drain 56b (coupled to VCC), a drift region 22b, a gate 42b, an oxide layer 71b, as well as a source 64b and a back-gate 65b formed in a p-well 18b, where the circuit connections of the n-buried layers 8a and 8b, as well as of the transistors T1 and T2 from FIG. 1A are shown in dashed lines in FIG. 1B.
As seen in FIG. 1B, the parasitic back-gate diode D1 results from the PN junction between the P-BASE region 6a and the drift region 22a. Moreover, the provision of the isolation buried layer 8a in the low-side device T1 leads to formation of the parasitic NPN transistor 44 with an emitter in the n-drift region 22s, a base in the P-BASE 6a, and a collector in the n-buried layer 8a. For low-side devices, such as the DENMOS device T1, the buried layer 8a advantageously isolates the drain 56a, to help minimize minority injection into the substrate 4. Also of note in FIG. 1B is the very slight overlap of the gate 42a and the thin RESURF drift region 22a, which is only about 0.2 to 0.3 um or less in conventional thin RESURF DEMOS devices. This small spatial overlap causes the gate-to-drain capacitance (Cgd) to be small for conventional thin RESURF DEMOS devices, advantageously allowing fast switching operation. However, the small overlap distance may lead to significant degradation in device parameters due to hot carrier injection into the drain-side end of the gate. Such hot carrier degradation reduces the reliability and thus lowers the useful life of the DEMOS T1. Accordingly, there is a need for improved drain-extended transistors with better performance reliability.